The invention relates to bit/column latches, and more particularly to a bit latch that can operate at a low Vcc.
FIGS. 1A and 1B show a circuit diagram of a typical 64K bit EEPROM 100 (Electrically Erasable Programmable Read Only Memory) of prior art. EEPROM 100 comprises an array of memory blocks 50. Each memory blocks 50 has 8 memory cells 1,2. Each memory cell 1,2 has a select transistor 1 and a memory transistor 2. Each select transistor 1 has its drain connected to a bit line 3, its gate connected to word line 4, and its source connected to the drain of a memory transistor 2 in the same memory cell 1,2. Each memory transistor 2 has its source grounded, its drain connected to the source of a select transistor 1 in the same memory cell 1,2, and its gate connected to an erase transistor 13. There is an erase transistor 13 associated with each memory block 50. Each erase transistor 13 has its drain connected to a control gate line 11, its source connected to the control gates of the eight memory transistors 2 of the associated memory block 50, and its gate connected to a word line 4. Each bit line 3 connects, at one end, to a high voltage charge pump 16 and a bit latch 18, and at the other end to an I/O line of data bus 8 via a Y-transistor 6. The gate of each Y-transistor 6 is connected to a Y-decoder 9 via a Y gate line 7. Y decoder 9 selects only one Y gate line 7 at a time. Each control gate line 11 connects, at one end, to a high voltage charge pump 22 and a bit latch 24, and at the other end to a control gate (CG) line 12 via a Y-transistor 10.
The programming (writing) operation of EEPROM 100 is carried out in a page mode in which 16 memory blocks 50 on a same word line 4 are programmed simultaneously. Programming cycle starts with CG line 12 being raised to Vcc (5V) and the program data intended for a memory block 50 (say, B0,0) appearing on eight lines of data bus 8. Y decoder 9 should select the rightmost Y gate line 7 because data on data bus 8 is intended for memory block B0,0. As a result, all eight Y transistors 6 corresponding to the first row of memory blocks 50 (i.e., B0,0; B0,1; . . . ) are ON passing the data intended for memory block B0,0 along eight bit lines 3 into eight bit latches 18 in FIG. 1B. FIG. 1B shows only the top one of the eight bit latches 18 corresponding to the first row of memory blocks 50.
Similarly, Y transistors 10 corresponding to the first row of memory blocks 50 (i.e., B0,0; B0,1; . . . ) are ON passing a high signal (Vcc) from CG line 12 along control gate line 11 into bit latch 24 in FIG. 1B corresponding to the first row of memory blocks 50. Each of bit latches 18 and 24 comprises a pair of cross-coupled CMOS inverters and a reset transistor.
Next, the same process occurs for memory block B1,0 (not shown). That is, CG line 12 is high (Vcc). Data intended for memory block B1,0 appears on data bus 8. Y decoder 9 selects the Y gate line 7 corresponding to the second row of memory blocks 50 to which memory block B1,0 belongs. As a result, all eight Y transistors 6 corresponding to the second row of memory blocks 50 (i.e., B1,0; B1,1; . . . ) are ON passing the data intended for memory block B1,0 along eight bit lines 3 into eight bit latches 18 (not shown) corresponding to the second row of memory blocks 50.
Similarly, Y transistors 10 corresponding to the second row of memory blocks 50 (i.e., B1,0; B1,1; . . . ) are ON passing a high signal (Vcc) from CG line 12 along control gate line 11 into bit latch 24 (not shown) corresponding to the second row of memory blocks 50. The same latching process occurs for other 14 rows such that data intended for 16 memory blocks B0,0; B1,0; B2,0; . . . and B15,0 are stored in 128 bit latches 18.
Next, simultaneously, all 16 high voltage charge pumps 22 corresponding to 16 rows of memory blocks 50 raise the potentials of the associated control gate lines 11 to an erasing level (20V). In the mean time, X decoder 5 selects the word line 4 corresponding to memory blocks B0,0; B10; B2,0; . . . ; and B15,0. As a result, all 128 memory cells 1,2 of the 16 memory blocks 50 are simultaneously erased.
Then, actual programming is simultaneously carried out for all 128 memory cells 1,2 of the 16 memory blocks B0,0; B1,0; B2,0; . . . ; and B15,0. Considering the top memory cell 1,2 of memory block B0,0, if its associated bit latch 18 stores a xe2x80x98highxe2x80x99, that is NMOS transistors 42 and PMOS transistor 48 are OFF, and NMOS transistors 46 and PMOS transistor 44 are ON, then node N1 has a high potential (Vcc), and transistor 19 is ON. As a result, the associated high voltage charge pump 16 operates to raise node N1 to a programming level (20V) thereby programming the top memory cell 1,2 of memory block B0,0.
On the other hand, if the bit latch 18 associated with the top memory cell 1,2 of memory block B0,0 stores a xe2x80x98lowxe2x80x99, that is NMOS transistors 42 and PMOS transistor 48 are ON, and NMOS transistors 46 and PMOS transistor 44 are OFF, then node N1 has a low potential (0V), and transistor 19 is OFF. As a result, the associated high voltage charge pump 16 does not operate and the top memory cell 1,2 of memory block B0,0 remains being erased. The other 127 memory cells 1,2 of the memory page including a first column of 16 memory blocks 50 are programmed in the same manner and at the same time.
After that, the second page including 16 memory blocks B0,1; B1,1; . . . ; and B15,1 is programmed in the same manner as the first page. As the size of memory cells decreases, the operating voltage for the memory circuits also decreases. As the operating voltage is reduced below 2V, some operating problems develop. For example, assuming 1.4V and 0V represent a xe2x80x98highxe2x80x99 and xe2x80x98lowxe2x80x99, respectively, on data bus 8, then EEPROM 100 may not operate correctly. With a threshold voltage drop of 0.7V across Y transistors 6, a xe2x80x98highxe2x80x99 of bit line 3 results in a voltage of 0.7V (1.4Vxe2x88x920.7V). This may not be high enough to switch the state of the associated bit latch 18.
For instance, consider the bit latch 18 associated with the top memory cell 1,2 in FIGS. 1A and 1B. Initially, the bit latch 18 is reset by turning ON reset transistor 17. As a result, bit latch 18 stores a xe2x80x98lowxe2x80x99, meaning NMOS transistors 42 and PMOS transistor 48 are ON, and NMOS transistors 46 and PMOS transistor 44 are OFF. With only 1.4V on an I/O line 8, it is difficult to overcome strongly conducting NMOS 42 to raise the potential of bit line 3 high enough to turn on NMOS transistor 46 so as to switch the state of bit latch 18 (making it store a xe2x80x98highxe2x80x99). Using a weak NMOS 42 would help make it easier to switch the state of bit latch 18 to xe2x80x98highxe2x80x99 but would result in bit latch 18 being unstable when bit line 3 later rises to the programming level (20V).
Therefore, it is an object of the present invention to introduce a bit latch that can be easily switched to xe2x80x98highxe2x80x99 but is still stable when bit line 3 later rises to the programming level (20V).
The present invention achieves the stated object by using a bit latch having a control transistor in series with the two transistors 44 and 42 of inverter 26 in FIG. 1B. When a xe2x80x98highxe2x80x99 needs to be stored in latch 18, the control transistor is turned on barely to weaken NMOS transistor 42. As a result, a xe2x80x98highxe2x80x99 data bit on bit line 3 can more easily turn on NMOS transistor 46 of inverter 27 triggering the switch in state of bit latch 18 to xe2x80x98highxe2x80x99. After that, the control transistor is strongly turned on and therefore it becomes transparent to the latch. As a result, the latch is stable when the bit line later ramps up to the high programming level.